In these days, as the high development in the information related industry and the need for information products with high operation and transmission speed increasingly, the industries may be forced to devote themselves in developing various transmission interface requirements. In terms of the storage interface, from the ATA (Advanced Technology Attachment) interface with a transmission rate of 16 MBps in the early phase, through the ATA33 interface with a transmission rate of 33 MBps, and the ATA66 interface with a transmission rate of 66 MBps, until the ATA 100 and ATA133 interface requirements, etc., all of them are confined by parallel data transmission, such that the amount of the signal lines used for transmission, the noise interference, the limitation on the length of the transmission lines, and the difficulty for raising the transmission rate are greater in the aforementioned interface requirements.
Recently, a serial ATA interface requirement is presented owing to several industries with unceasing attempts. Whereby, not only the transmission rate is raised beyond 1.5 GBps in the first generation at one stroke, but also the second generation with the transmission rate of 3 GBps and even the third generation with that of 6.0 GBps are all just around the corner. Moreover, the only four signal lines being required for data transmission, and the greatly lengthened signal lines, are all significant progress.
Moreover, the product with serial ATA interface requirement is still under developed, and that with parallel ATA is yet mainstream. For the purpose of expansion as well as adaptation both, the design in the computer system is essentially capable of supporting two interface requirements.
In the past, there is an attempt for adding a serial ATA physical layer (PHY) into the storage medium controller provided in the main control chip, by which a serial ATA device is connected. However, a larger area must be occupied by the serial ATA physical layer including a high frequency analog circuit, such that the area of the main control chip will excessively large and the yield rate thereof may be hard to control, when the serial ATA physical layer is intended to be integrated into the main control chip (for example, south bridge chip).
Another solution proposed by the industry is shown in FIG. 1, wherein a part of circuit in the serial ATA physical layer is made independently in a serial ATA external physical layer 161. A storage medium controller 121 in a main control chip 12 may be connected to a serial ATA device 16 (a serial ATA hard disk, for instance) via the serial ATA external physical layer 161, other than connected to a parallel ATA device 18 (a parallel ATA hard disk, for example) via an Integrated Drive Electronics (IDE) bus 14.
Although the aforementioned problem may be solved by this configuration, the connection pins must be added on the main control chip 12 for connecting with the external physical layer, resulting in an increased cost. Additionally, the slot and the circuit of the main board are also required to be redesigned entirely, causing bothering the industry.